module wb_stage (
  input         clk,
  input         rst_n,
  input         mem_wb_vld,
  input         mem_wb_is_opload,
  input [4:0]   mem_wb_rd,
  input [31:0]  mem_wb_rd_data,
  input [31:0]  mem_wb_mrdata,

  output reg        wb_id_rd_wena,
  output reg [4:0]  wb_id_rd,
  output reg [31:0] wb_id_rd_data
);

  always @(posedge clk, negedge rst_n) begin
    if (~rst_n) begin
      wb_id_rd_wena <= 1'b0;
      wb_id_rd <= 5'b0;
      wb_id_rd_data <= 32'b0;
    end else begin
      wb_id_rd_wena <= mem_wb_vld;
      if (mem_wb_vld) begin
        wb_id_rd <= mem_wb_rd;
        wb_id_rd_data <= mem_wb_is_opload? mem_wb_mrdata: mem_wb_rd_data;
      end
    end
  end

endmodule

